During a design verification test, circuit design models are tested for verifying their functionality and functional behavior at error conditions as well as normal operation conditions. Typically, test vectors generated by testbenches, automatic test equipment (ATE), or actual target devices are fed to the circuit design implemented in a functional simulator, a hardware-based simulation accelerator, or a hardware emulator to capture erratic or unintended behavior violated by the circuit design during the design verification test. The erratic or unintended behavior observed during the verification test is carefully analyzed, and the circuit design is corrected if necessary and tested until it behaves as intended without identifiable errors.
Full functional verification of a circuit design requires testing under all possible conditions to ensure that all design paths are completely simulated and hence verified. Failure to test all design paths may result in a critical bug that is not discovered before the circuit design is finalized. Complex circuits typically require a very large number of tests to accomplish full functional verification, resulting in a very long verification test time. Additionally, the generation of large test suites is subject to errors or missed test conditions.
Functional circuit design verification must also include verification of the system and software interaction with the design, including responses to error conditions. This verifies correct detection and reporting of an error condition by the circuit and the system's correct responsiveness to the detected error condition.
The coverage by the verification test can be enhanced by including tests that are targeted to exercise specific paths within the circuit design. In some cases, knowledge of internal design states and parameters is needed to define test cases.
For testing error handling and recovery capability of a circuit design, errors are intentionally produced and injected to test the behavior of the circuit design under error conditions, preferably in real data traffic to define flag-specific events in the circuit design during the test.
Several approaches have been made to verify user designs in test cases. User designs can be verified in a pure simulation or hardware-based simulation acceleration environment, oftentimes in conjunction with a testbench that generates data streams and test cases. Alternatively, user designs can be modeled and run in an emulator, FPGAs, hardware prototyping system, or other systems as connected to a real target system generating real data streams. Error injectors are used to expand a number of test cases to which the circuit design is exposed by injecting errors into the circuit's input data streams during a design verification test. Test results are obtained and compared to the expected behavior.
In a simulation or simulation-acceleration environment, test data is generated by testbenches that model the functional behavior of other devices in a target environment. The characteristics of the modeled devices and the test data that they generate generally differ from those of actual target devices at some level. Therefore, simulation and simulation-acceleration cannot directly verify circuit design behavior under actual target conditions.
Additionally, tests in simulation or simulation acceleration are run orders of magnitude slower than normal operating speed. This limits their usability for system-level and driver-level software verification. Consequently, these environments cannot fully verify the interaction of circuit designs with software, including error detection, response, and recovery.
Error injectors running with emulators, rapid prototyping systems, or FPGAs also have limitations. The commercially available error injectors have no visibility of the internal conditions of the design itself. Therefore, they can only inject errors based only on external conditions of the design, such as protocol conditions or data conditions that are observable externally.
The present invention overcomes the above-identified shortcomings of prior art error injecting techniques and provides benefits and solutions by dynamically injecting errors to a user design based on internal design conditions for the purpose of testing error cases during a design verification test.